1. Field of the Invention
The present invention relates to a control method and clock data recovery device thereof for generating a recovery clock, and more particularly, to a control method and clock data recovery device thereof capable of generating an accurate recovery clock without using an accurate reference clock.
2. Description of the Prior Art
In an electronic system, clock signals between a transmitting end and a receiving end inherently have a clock skew. The electronic system needs to utilize a clock data recovery circuit for compensating the clock skew between the clock signals, so as to correctly acquire transmission data at the receiving end. The clock data recovery circuit needs an accurate reference clock for precisely compensating the clock skew.
Please refer to FIG. 1, which is a schematic diagram of a conventional clock data recovery device 10. The clock data recovery device 10 is utilized for generating a recovery clock CLK and retimed data RDATA according to an input data stream DATAIN and a reference clock REF. As shown in FIG. 1, the clock data recovery device 10 includes a phase detector PDET, a frequency detector FDET, a selecting unit SEL, a state machine STA, a charge pump CP, a low-pass filter LPF, a multi-bands voltage-controlled oscillator VCO and a frequency dividing unit DIV. The phase detector PDET is utilized for detecting a phase difference between a data frequency of the input data stream DATAIN and the recovery clock CLK outputted by the multi-bands voltage-controlled oscillator VCO and accordingly generating a phase difference signal S_PD and a phase locking signal DLOCK. The phase detector PDET is also utilized for generating the retimed data RDATA according to the input data stream DATAIN and the recovery clock CLK. The phase detector PDET may include a d-flip-flop and a serial-to-parallel converter. The d-flip-flop is utilized for correcting the data frequency of the input data stream DATAIN. The serial-to-parallel converter then converts the corrected input data stream DATAIN for generating the retimed data RDATA. The frequency detector FDET is utilized for determining a frequency difference between the reference clock REF and a dividing clock DIVCLK generated by the dividing unit DIV, to accordingly generate a frequency difference signal S_FD and a frequency locking signal FLOCK. The selecting unit SEL is utilized for outputting one of the phase difference signal S_PD and the frequency difference signal S_FD to the charge pump CP according to a control signal CON. The charge pump CP is utilized for generating a current signal CC to the low-pass filter LPF according to the signal outputted by the selecting unit SEL. The low-pass filter LPF generates a corresponding locking voltage VC according to the current signal CC. The multi-bands voltage-controlled oscillator VCO generates the recovery clock CLK according to the locking voltage VC. The state machine STA is utilized for outputting the selecting control signal CON to the selecting unit SEL according to the phase locking signal DLOCK and the frequency locking signal FLOCK.
The clock data recovery device 10 first makes the frequency of the recovery clock CLK track that of the reference clock REF. In such a condition, the state machine STA controls the selecting unit SEL to output the frequency difference signal S_FD via adjusting the selecting control signal CON. When the frequency of the recovery clock CLK is close to the reference clock REF, the frequency detector FDET outputs the appropriate frequency locking signal FLOCK, for allowing the state machine STA to control the selecting unit SEL to output the phase difference signal S_PD. Via two-stages locking and the precise reference clock REF, the clock data recovery can avoid mis-lock occurring, and acquire the accurate recovery clock CLK and the re-timed data according to the input data stream DATAIN.
The reference clock REF needs to be optimized and of low jitter for preventing the clock data recovery device 10 from going into mis-lock while performing the locking procedures. Moreover, the input data stream DATAIN is required to include a training pattern when the clock data recovery device 10 begins to work, for accurately acquiring the retimed data RDATA.